In the analogue simulation core global nodes (e.g.The build system now implements an additional install step for MacOSX and the appropriate icons. US letter formats for schematic frame have been added. Simulation time for digital files (Verilog and VHDL) are now stored in an additional configuration file and the import dialog has been replaced by a complete import/export frontend for the Qucs-Converter command line tool. Passing parameters to Verilog-HDL and VHDL subcircuits and typed generic parameters of VHDL files are now supported as well as arbitrary in/out signals.
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